Публикации
Патент
DETECTION OF ADDRESS ERRORS IN MEMORY DEVICES USING MULTI-SEGMENT ERROR DETECTION CODES
2021
Статья
Memory Physical Aware Multi-Level Fault Diagnosis Flow
2020
700-711
Статья
Fault Awareness for Memory BIST Architecture Shaped by Multidimensional Prediction Mechanism
2019
562-575
Патент
FINFET-BASED MEMORY TESTING USING MULTIPLE READ OPERATIONS
2019
Статья
Experimental study on Hamming and Hsiao Codes in the Context of Embedded Applications
2017
25-28
Статья
Automated Flow for Test Pattern Creation for IPs in SoC
2017
21-24
Статья
An Efficient Testing Methodology for Embedded Flash Memories
2017
422-425
Статья
Security Issues in Test and Repair Infrastructure for Systems-on-Chip
2017
114-122
Патент
Testing Electronic Memories Based on Fault and Test Algorithm Periodicity
2017
Конференция
A power based memory BIST grouping methodology.
2015
27-30
Конференция
Overview study on fault modeling and test methodology development for FinFET-based memories.
2015
19-22
Конференция
Extending fault periodicity table for testing faults in memories under 20nm.
2014
5-9